Index: apps/plugins/plugin.lds =================================================================== --- apps/plugins/plugin.lds (revision 16974) +++ apps/plugins/plugin.lds (working copy) @@ -16,6 +16,23 @@ #define STUBOFFSET 0 #endif +#if defined(CPU_PP) +#define CACHEALIGN_SIZE 16 +#if NUM_CORES > 1 +#ifdef CPU_PP502x +#define NOCACHE_BASE 0x10000000 +#else +#define NOCACHE_BASE 0x28000000 +#endif +#else +#endif +#endif + +#ifndef NOCACHE_BASE +/* Default to no offset */ +#define NOCACHE_BASE 0x00000000 +#endif + #if CONFIG_CPU==S3C2440 #include "s3c2440.h" #define DRAMSIZE (MEMORYSIZE * 0x100000) - 0x100 - PLUGIN_BUFFER_SIZE - STUBOFFSET - CODEC_SIZE - LCD_BUFFER_SIZE - TTB_SIZE @@ -119,10 +136,20 @@ .data : { *(.data*) + } > PLUGIN_RAM + +#if NOCACHE_BASE != 0 + .ncdata . + NOCACHE_BASE : + { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncdata*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> PLUGIN_RAM +#endif + #if defined(IRAMSIZE) - iramcopy = .; + iramcopy = . - NOCACHE_BASE; #endif - } > PLUGIN_RAM /DISCARD/ : { @@ -139,6 +166,7 @@ iramend = .; } > PLUGIN_IRAM + .ibss (NOLOAD) : { iedata = .; @@ -150,13 +178,27 @@ .bss (NOLOAD) : { - plugin_bss_start = .; + plugin_bss_start = .; *(.bss*) *(COMMON) . = ALIGN(0x4); + } > PLUGIN_RAM + +#if NOCACHE_BASE != 0 + .ncbss . + NOCACHE_BASE (NOLOAD) : + { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncbss*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> PLUGIN_RAM +#endif + + /* Restore . */ + .pluginend . - NOCACHE_BASE : + { _plugin_end_addr = .; plugin_end_addr = .; - } > PLUGIN_RAM + } /* Special trick to avoid a linker error when no other sections are left after garbage collection (plugin not for this platform) */ Index: firmware/export/config.h =================================================================== --- firmware/export/config.h (revision 16974) +++ firmware/export/config.h (working copy) @@ -457,7 +457,6 @@ and not a special semaphore instruction */ #define CORELOCK_SWAP 2 /* A swap (exchange) instruction */ -/* Dual core support - not yet working on the 1G/2G and 3G iPod */ #if defined(CPU_PP) #define IDLE_STACK_SIZE 0x80 #define IDLE_STACK_WORDS 0x20 @@ -466,16 +465,14 @@ #define NUM_CORES 2 #define CURRENT_CORE current_core() -/* Use IRAM for variables shared across cores - large memory buffers should - * use UNCACHED_ADDR(a) and be appropriately aligned and padded */ -#define NOCACHEBSS_ATTR IBSS_ATTR -#define NOCACHEDATA_ATTR IDATA_ATTR +#define NOCACHEBSS_ATTR __attribute__ ((section(".ncbss"),nocommon)) +#define NOCACHEDATA_ATTR __attribute__ ((section(".ncdata"),nocommon)) #define IF_COP(...) __VA_ARGS__ #define IF_COP_VOID(...) __VA_ARGS__ #define IF_COP_CORE(core) core -#if CONFIG_CPU == PP5020 || CONFIG_CPU == PP5002 +#ifdef CPU_PP #define CONFIG_CORELOCK SW_CORELOCK /* SWP(B) is broken */ #else #define CONFIG_CORELOCK CORELOCK_SWAP Index: firmware/target/arm/system-target.h =================================================================== --- firmware/target/arm/system-target.h (revision 16974) +++ firmware/target/arm/system-target.h (working copy) @@ -108,7 +108,7 @@ /* Certain data needs to be out of the way of cache line interference * such as data for COP use or for use with UNCACHED_ADDR */ #define PROC_NEEDS_CACHEALIGN -#define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */ +#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ /** cache functions **/ #ifndef BOOTLOADER Index: firmware/target/arm/olympus/app.lds =================================================================== --- firmware/target/arm/olympus/app.lds (revision 16974) +++ firmware/target/arm/olympus/app.lds (working copy) @@ -21,6 +21,17 @@ #define IRAMORIG 0x40000000 #define IRAMSIZE 0xc000 +#if NUM_CORES > 1 +#ifdef CPU_PP502x +#define NOCACHE_BASE 0x10000000 +#else +#define NOCACHE_BASE 0x28000000 +#endif +#define CACHEALIGN_SIZE 16 +#else +#define NOCACHE_BASE 0x00000000 +#endif + /* End of the audio buffer, where the codec buffer starts */ #define ENDAUDIOADDR (DRAMORIG + DRAMSIZE) @@ -70,6 +81,18 @@ _dataend = .; } > DRAM +#if NOCACHE_BASE != 0 + /* .ncdata section is placed at uncached physical alias address and is + * loaded at the proper cached virtual address - no copying is + * performed in the init code */ + .ncdata . + NOCACHE_BASE : + { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncdata*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + /DISCARD/ : { *(.eh_frame) @@ -103,7 +126,7 @@ _iend = .; } > IRAM - .idle_stacks : + .idle_stacks (NOLOAD) : { *(.idle_stacks) #if NUM_CORES > 1 @@ -116,7 +139,7 @@ cop_idlestackend = .; } > IRAM - .stack : + .stack (NOLOAD) : { *(.stack) stackbegin = .; @@ -124,37 +147,53 @@ stackend = .; } > IRAM - .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors): + /* .bss and .ncbss are treated as a single section to use one init loop to + * zero it - note "_edata" and "_end" */ + .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\ + SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) : { _edata = .; *(.bss*) *(COMMON) . = ALIGN(0x4); - _end = .; } > DRAM - .audiobuf ALIGN(4) : +#if NOCACHE_BASE != 0 + .ncbss . + NOCACHE_BASE (NOLOAD): { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncbss*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + + /* This will be aligned by preceding alignments */ + .endaddr . - NOCACHE_BASE (NOLOAD) : + { + _end = .; + } > DRAM + + .audiobuf (NOLOAD) : + { _audiobuffer = .; audiobuffer = .; } > DRAM - - .audiobufend ENDAUDIOADDR: + + .audiobufend ENDAUDIOADDR (NOLOAD) : { audiobufend = .; _audiobufend = .; } > DRAM - .codec ENDAUDIOADDR: + .codec ENDAUDIOADDR (NOLOAD) : { codecbuf = .; _codecbuf = .; } - .plugin ENDADDR: + .plugin ENDADDR (NOLOAD) : { _pluginbuf = .; pluginbuf = .; } } - Index: firmware/target/arm/ipod/app.lds =================================================================== --- firmware/target/arm/ipod/app.lds (revision 16974) +++ firmware/target/arm/ipod/app.lds (working copy) @@ -21,6 +21,17 @@ #define IRAMORIG 0x40000000 #define IRAMSIZE 0xc000 +#if NUM_CORES > 1 +#ifdef CPU_PP502x +#define NOCACHE_BASE 0x10000000 +#else +#define NOCACHE_BASE 0x28000000 +#endif +#define CACHEALIGN_SIZE 16 +#else +#define NOCACHE_BASE 0x00000000 +#endif + /* End of the audio buffer, where the codec buffer starts */ #define ENDAUDIOADDR (DRAMORIG + DRAMSIZE) @@ -70,6 +81,18 @@ _dataend = .; } > DRAM +#if NOCACHE_BASE != 0 + /* .ncdata section is placed at uncached physical alias address and is + * loaded at the proper cached virtual address - no copying is + * performed in the init code */ + .ncdata . + NOCACHE_BASE : + { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncdata*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + /DISCARD/ : { *(.eh_frame) @@ -103,7 +126,7 @@ _iend = .; } > IRAM - .idle_stacks : + .idle_stacks (NOLOAD) : { *(.idle_stacks) #if NUM_CORES > 1 @@ -116,7 +139,7 @@ cop_idlestackend = .; } > IRAM - .stack : + .stack (NOLOAD) : { *(.stack) stackbegin = .; @@ -124,37 +147,53 @@ stackend = .; } > IRAM - .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors): + /* .bss and .ncbss are treated as a single section to use one init loop to + * zero it - note "_edata" and "_end" */ + .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\ + SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) : { _edata = .; *(.bss*) *(COMMON) . = ALIGN(0x4); - _end = .; } > DRAM - .audiobuf ALIGN(4) : +#if NOCACHE_BASE != 0 + .ncbss . + NOCACHE_BASE (NOLOAD): { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncbss*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + + /* This will be aligned by preceding alignments */ + .endaddr . - NOCACHE_BASE (NOLOAD) : + { + _end = .; + } > DRAM + + .audiobuf (NOLOAD) : + { _audiobuffer = .; audiobuffer = .; } > DRAM - - .audiobufend ENDAUDIOADDR: + + .audiobufend ENDAUDIOADDR (NOLOAD) : { audiobufend = .; _audiobufend = .; } > DRAM - .codec ENDAUDIOADDR: + .codec ENDAUDIOADDR (NOLOAD) : { codecbuf = .; _codecbuf = .; } - .plugin ENDADDR: + .plugin ENDADDR (NOLOAD) : { _pluginbuf = .; pluginbuf = .; } } - Index: firmware/target/arm/sandisk/app.lds =================================================================== --- firmware/target/arm/sandisk/app.lds (revision 16974) +++ firmware/target/arm/sandisk/app.lds (working copy) @@ -21,6 +21,17 @@ #define IRAMORIG 0x40000000 #define IRAMSIZE 0xc000 +#if NUM_CORES > 1 +#ifdef CPU_PP502x +#define NOCACHE_BASE 0x10000000 +#else +#define NOCACHE_BASE 0x28000000 +#endif +#define CACHEALIGN_SIZE 16 +#else +#define NOCACHE_BASE 0x00000000 +#endif + /* End of the audio buffer, where the codec buffer starts */ #define ENDAUDIOADDR (DRAMORIG + DRAMSIZE) @@ -70,6 +81,18 @@ _dataend = .; } > DRAM +#if NOCACHE_BASE != 0 + /* .ncdata section is placed at uncached physical alias address and is + * loaded at the proper cached virtual address - no copying is + * performed in the init code */ + .ncdata . + NOCACHE_BASE : + { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncdata*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + /DISCARD/ : { *(.eh_frame) @@ -103,7 +126,7 @@ _iend = .; } > IRAM - .idle_stacks : + .idle_stacks (NOLOAD) : { *(.idle_stacks) #if NUM_CORES > 1 @@ -116,7 +139,7 @@ cop_idlestackend = .; } > IRAM - .stack : + .stack (NOLOAD) : { *(.stack) stackbegin = .; @@ -124,37 +147,53 @@ stackend = .; } > IRAM - .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors): + /* .bss and .ncbss are treated as a single section to use one init loop to + * zero it - note "_edata" and "_end" */ + .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\ + SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) : { _edata = .; *(.bss*) *(COMMON) . = ALIGN(0x4); - _end = .; } > DRAM - .audiobuf ALIGN(4) : +#if NOCACHE_BASE != 0 + .ncbss . + NOCACHE_BASE (NOLOAD): { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncbss*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + + /* This will be aligned by preceding alignments */ + .endaddr . - NOCACHE_BASE (NOLOAD) : + { + _end = .; + } > DRAM + + .audiobuf (NOLOAD) : + { _audiobuffer = .; audiobuffer = .; } > DRAM - - .audiobufend ENDAUDIOADDR: + + .audiobufend ENDAUDIOADDR (NOLOAD) : { audiobufend = .; _audiobufend = .; } > DRAM - .codec ENDAUDIOADDR: + .codec ENDAUDIOADDR (NOLOAD) : { codecbuf = .; _codecbuf = .; } - .plugin ENDADDR: + .plugin ENDADDR (NOLOAD) : { _pluginbuf = .; pluginbuf = .; } } - Index: firmware/target/arm/iriver/app.lds =================================================================== --- firmware/target/arm/iriver/app.lds (revision 16974) +++ firmware/target/arm/iriver/app.lds (working copy) @@ -21,6 +21,17 @@ #define IRAMORIG 0x40000000 #define IRAMSIZE 0xc000 +#if NUM_CORES > 1 +#ifdef CPU_PP502x +#define NOCACHE_BASE 0x10000000 +#else +#define NOCACHE_BASE 0x28000000 +#endif +#define CACHEALIGN_SIZE 16 +#else +#define NOCACHE_BASE 0x00000000 +#endif + /* End of the audio buffer, where the codec buffer starts */ #define ENDAUDIOADDR (DRAMORIG + DRAMSIZE) @@ -70,6 +81,18 @@ _dataend = .; } > DRAM +#if NOCACHE_BASE != 0 + /* .ncdata section is placed at uncached physical alias address and is + * loaded at the proper cached virtual address - no copying is + * performed in the init code */ + .ncdata . + NOCACHE_BASE : + { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncdata*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + /DISCARD/ : { *(.eh_frame) @@ -103,7 +126,7 @@ _iend = .; } > IRAM - .idle_stacks : + .idle_stacks (NOLOAD) : { *(.idle_stacks) #if NUM_CORES > 1 @@ -116,7 +139,7 @@ cop_idlestackend = .; } > IRAM - .stack : + .stack (NOLOAD) : { *(.stack) stackbegin = .; @@ -124,37 +147,53 @@ stackend = .; } > IRAM - .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors): + /* .bss and .ncbss are treated as a single section to use one init loop to + * zero it - note "_edata" and "_end" */ + .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\ + SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) : { _edata = .; *(.bss*) *(COMMON) . = ALIGN(0x4); - _end = .; } > DRAM - .audiobuf ALIGN(4) : +#if NOCACHE_BASE != 0 + .ncbss . + NOCACHE_BASE (NOLOAD): { + . = ALIGN(CACHEALIGN_SIZE); + *(.ncbss*) + . = ALIGN(CACHEALIGN_SIZE); + } AT> DRAM +#endif + + /* This will be aligned by preceding alignments */ + .endaddr . - NOCACHE_BASE (NOLOAD) : + { + _end = .; + } > DRAM + + .audiobuf (NOLOAD) : + { _audiobuffer = .; audiobuffer = .; } > DRAM - - .audiobufend ENDAUDIOADDR: + + .audiobufend ENDAUDIOADDR (NOLOAD) : { audiobufend = .; _audiobufend = .; } > DRAM - .codec ENDAUDIOADDR: + .codec ENDAUDIOADDR (NOLOAD) : { codecbuf = .; _codecbuf = .; } - .plugin ENDADDR: + .plugin ENDADDR (NOLOAD) : { _pluginbuf = .; pluginbuf = .; } } -